CFET
CFET – Complementary Field-Effect Transistor
CFET (Complementary Field-Effect Transistor) is a next-generation transistor architecture proposed to succeed FinFET and GAA (Gate-All-Around) FET technologies in sub-3nm and beyond semiconductor nodes. It offers vertical stacking of N-type and P-type transistors on a single device footprint, enabling further transistor scaling, improved performance, and reduced chip area — all critical for advancing Moore’s Law.
CFET is a promising solution to extend CMOS scaling without compromising drive strength or increasing parasitics.
Structure:
The CFET architecture integrates:
- A vertically stacked configuration of N-type (nFET) and P-type (pFET) transistors.
- Each FET uses a GAA nanowire or nanosheet structure for tight electrostatic control.
- Independent gate control, source, and drain contacts for both nFET and pFET.
- Isolation between the top and bottom FET layers via interlayer dielectric (ILD) and metal vias.
In typical designs:
- The nFET is fabricated above the pFET (or vice versa) using advanced 3D integration techniques.
- Selective epitaxy, etching, and deposition processes enable clean stacking and isolation.
Working Principle:
Each transistor (nFET and pFET) operates like a conventional GAA nanosheet/nanowire FET, but:
- They are built in different vertical planes, sharing the same lateral footprint.
- The GAA structure ensures strong gate control over the channel.
- Independent biasing and switching are maintained using dedicated gate stacks and metal routing.
The key innovation is in monolithic 3D integration without degrading performance, enabling true CMOS logic in an ultra-compact form.
Advantages of CFET Technology:
- Ultimate CMOS scaling: Reduces standard cell height by vertically integrating complementary devices.
- Higher device density: Nearly 2× improvement over traditional GAA/FinFETs.
- Lower interconnect parasitics: Shorter gate-to-gate paths reduce delay and power.
- Better performance-power-area (PPA) balance.
- Continues Moore’s Law when 2D scaling reaches limits.
Challenges & Innovations:
Implementing CFETs requires overcoming advanced fabrication challenges:
- Precise vertical alignment and doping of stacked layers
- Thermal budget management to avoid degradation
- Selective epitaxy and etch-stop layer engineering
- Gate isolation and metal routing for separate nFET/pFET control
Foundries and research labs are actively developing CFET process flows using buried channel formation, bottom-up fabrication, and advanced metrology.
Applications:
- High-density logic circuits (mobile SoCs, CPUs, GPUs)
- Advanced AI/ML processors with strict PPA targets
- Low-power IoT and edge computing devices
- 3D-stacked chiplets and monolithic integration platforms
Our CFET Development Services:
We support leading-edge CFET research and development through:
- 3D TCAD Simulation for stacked nFET/pFET architectures
- Process flow design and validation (GAA, epitaxy, interlayer isolation)
- Custom layout and cell library generation for CFET standard cells
- EDA integration support for CFET-based design rule development
- Prototype fabrication consulting including nanosheet release, etching, and gate-stack formation