SRAM
6T SRAM – 6-Transistor Static Random-Access Memory
The 6T SRAM (Static Random-Access Memory) cell is the most commonly used architecture for high-speed, low-power volatile memory in modern processors, cache systems, and SoCs. It consists of six transistors per bit cell and offers fast access time, low leakage power, and excellent stability across PVT (process-voltage-temperature) variations.
Used extensively in L1/L2/L3 CPU caches, GPU memory, register files, and embedded memory applications, the 6T SRAM cell is a cornerstone of modern VLSI design.
Structure:
A standard 6T SRAM cell includes:
- 2 cross-coupled inverters (4 transistors: M1–M4) forming a bistable latch that holds the binary data (either ‘0’ or ‘1’)
- 2 access (pass) transistors (M5 and M6) that connect the internal storage nodes to the bitlines (BL and BLB) during read/write operations
- Wordline (WL) controls the access transistors
- Bitlines (BL and BLB) carry data to and from the cell
Transistor Roles:
- M1, M3 = Pull-down NMOS transistors
- M2, M4 = Pull-up PMOS transistors
- M5, M6 = NMOS access transistors
Working Principle:
Write Operation:
- Data to be written is placed on BL and BLB (complementary).
- WL is activated, turning on the access transistors.
- The stronger bitline driver overwrites the internal nodes to store the new data.
Read Operation:
- BL and BLB are precharged to VSS & DD.
- WL is asserted, and one of the bitlines is pulled down depending on stored value.
- Sense amplifiers detect the differential signal to read the bit.
Hold Mode:
- WL is low, access transistors are off.
- Cross-coupled inverters retain the data without refresh, as long as power is supplied.
Key Features & Benefits:
- High speed (nanosecond access times)
- Low power consumption, especially in hold mode
- No need for refresh (unlike DRAM)
- Read/Write repeatability over millions of cycles
- Scalable array integration for cache and embedded memory
- Robust against soft errors compared to DRAM
Design Considerations:
- Read stability (SNM – Static Noise Margin)
- Write ability: Strong enough bit line drivers vs cell feedback strength
- Cell ratio and pull-up ratio optimization for noise and performance
- Minimum sized layout for area efficiency
- Access transistor sizing for speed and leakage trade-off
Applications of 6T SRAM:
- On-chip cache (L1, L2, L3) in CPUs, GPUs, DSPs
- Microcontroller memory
- Mobile SoCs and low-power electronics
- AI/ML accelerators with embedded SRAM arrays
- Register files and lookup tables (LUTs) in FPGAs
Our 6T SRAM Support Services:
We provide comprehensive 6T SRAM solutions, including:
- Full SRAM cell design with transistor sizing and SPICE-level simulation
- Custom layout design (DRC/LVS clean, compact, foundry-compliant)
- SRAM array generation and tiling for memory compilers
- Performance analysis: SNM, I read, I hold, leakage, and delay
- Variation-aware simulation using Monte Carlo and corner analysis
- Integration with PDKs and standard cell libraries
- TCAD support for device-level modeling of SRAM transistors